10.9.1.4 CPU Address Error Trap

This trap will be taken when any of the following circumstances occur:

1. If a W-reg (W0 through W14) is used by an AGU as a source or destination and a misaligned data word access (long word access at an odd address or word access at an odd byte address) is attempted.
   Note: For misaligned writes, the read or write is not inhibited. Address alignment is forced such that read or write is always aligned.
2. If a W-reg (W0 through W15) is used by an AGU, and the address or offset pointed to by the W-reg is beyond 24 bits in size. In other words, an address error trap will be generated if the MSB of the address pointed to by the W-reg used by the AGU is not set to 8'h00, or if the MSB of the address offset pointed to by the W-reg, which is used for EA calculation, is not 8'h00 or 8'hFF.

   or

   as an offset where permitted and contains a value where the Most Significant 8 bits are neither 8’h00 or 8’hFF (the offset can be a signed negative value).
   Note: The CPU will detect X address access to SFRs and treat these as a special case. However, Y space reads of SFR or PS addresses must be detected by the BMX and result in an address error trap.
3. If the MSB of a computed PFC address (BRAW, RCALLW, CALLW, GOTOW) is not 8’h00.