29.4.4 Differential Input Mode

Differential Input Mode of Op Amp can be controlled by the DIFFCON bit in the AMPxCON1 register. The DIFFCON[1:0] bit field enables the user to disable operation of the PMOS and/or the NMOS input differential input pair of transistors in the amplifier so that they can be calibrated separately.

The Op Amp effectively combines the advantages of the PMOS and NMOS differential pairs for rail-to-rail input operation. The complementary pair inputs allow the common mode voltage to extend to the supply rails without phase inversion. These are used to design the input stage of single-supply, voltage-feedback amplifiers.

In the region near the V_SS, the offset error of the PMOS portion of the input stage is dominant and in the region near the V_DD, the offset error is dominated by the NMOS transistor pair. That is, as the input common-mode voltage increases from V_SS, the PMOS transistors go into the cutoff region and the input transitions to the NMOS transistors, which enables operation above the positive supply. With a complementary pair input stage, the PMOS transistors enable operation slightly below the negative supply and the NMOS transistors allow for operation slightly above the positive supply.

With the topology used, the amplifier effectively combines the advantages of the PMOS and NMOS transistors for true rail-to-rail input operation. When the input terminals of the amplifier are driven towards the negative rail, the PMOS transistors are turned ON and the NMOS transistors are completely OFF. Conversely, when the input terminals are driven to the positive rail the NMOS Transistors are ON and PMOS transistors are OFF. This choice of operation allows the users to trade input voltage range for improved INL and offset voltage operation.