20.4.14 I²Cx Host Bus Cumulative Time-out Register

Table 20-15. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	I2CxHBCTO
Offset:	0x18B4, 0x1904


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	HBCTOTMR[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	HBCTOTMR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	HBCTOTMR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 23:0 – HBCTOTMR[23:0] I²C Host Cumulative Bus Time-out Timer bits

Provides the Reset value for the HCBCTO timer. The timer resets on detection of a START or ACK or STOP and continued to run when SCL low is extended and HSTACT=1. The timer is disabled when HBCTE=0.

20.4.14 I2Cx Host Bus Cumulative Time-out Register

Bits 23:0 – HBCTOTMR[23:0] I2C Host Cumulative Bus Time-out Timer bits

20.4.14 I²Cx Host Bus Cumulative Time-out Register

Bits 23:0 – HBCTOTMR[23:0] I²C Host Cumulative Bus Time-out Timer bits