20.4.11 I²Cx Status Register

Note:

Cleared by any Stop detected on the bus. Cleared by I2CxSTAT2.BSCLTO or I2CxSTAT.BCL conditions. Cleared by any address match failure in 10-bit Addressing mode. Cleared by any address match failure following a Restart detect. Cleared when NACK is either received or transmitted to client. Cleared when client goes to IDLE after ACK/NACK CRC byte.
Cleared when BCL is set. Cleared when Stop is sent. Cleared for I2CxSTAT2.BSCLTO condition, after the host successfully sends a STOP condition.
It is the user’s responsibility to make sure the EOP = ”0” to start new packet transmission.
ERRF is combined Error Status bit of I2CxSTAT2.BSCLTO + I2CxSTAT2.CBCTO + I2CxSTAT2.HBCTO + I2CxSTAT2.FRAME + I2CxSTAT2.CRC + I2CxSTAT1.BCL + I2CxSTAT2.NACKE.

Table 20-12. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	I2CxSTAT2
Offset:	0x18A8, 0x18F8


Bit	31	30	29	28	27	26	25	24
	SSPND	CLTACT	HSTACT				HSBCL	EOP
Access	R/HS/HC	R/HS/HC	R/HS/HC				R/C/HS	R/C/HS
Reset	0	0	0				0	0


Bit	23	22	21	20	19	18	17	16
	BSCLTO	HBCLTO	CBCLTO	BITO	FRME	NACKE		CRC
Access	R/C/HS	R/C/HS	R/C/HS	R/C/HS	R/C/HS	R/C/HS		R/C/HS
Reset	0	0	0	0	0	0		0


Bit	15	14	13	12	11	10	9	8
	STOPE	STARTE	HSTIF	CLTIF	ERR
Access	R/C/HS	R/HSC	R/HSC	R/C/HSC	R/C/HSC
Reset	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
					SCLCNT[3:0]
Access					R/W/HS	R/W/HS	R/W/HS	R/W/HS
Reset					0	0	0	0

Bit 31 – SSPND I²C Suspended bit

During a host transaction, I²C bus activity is suspended to allow the user to service the I²C interrupt. During a client transaction, the SCL line is pulled low to clock stretch until the user services the I²C interrupt.

Value	Description
`1`	The I²C is in a suspended state
`0`	The I²C is not in a suspended state

Bit 30 – CLTACT Client State Machine Active Status bit

Value	Description
`1`	Set after the eighth falling SCL edge of a received matching client address
`0`	Client is idle⁽¹⁾

Bit 29 – HSTACT Host State Machine Active Status bit

Value	Description
`1`	Host mode state machine is active; set when host state machine asserts a Start on bus Under these conditions, the host function is enabled and a START/RESTART condition is sent on the I²C bus followed by data from the transmit buffer.
`0`	Host is Idle⁽²⁾

Bit 25 – HSBCL Host Stop Bus Collision Detect Flag bit

Value	Description
`1`	Host Stop Bus Collision is detected
`0`	Host Stop Bus Collision is not detected

Bit 24 – EOP End-of-Packet Flag bit⁽³⁾

Value	Description
`1`	End of packet condition detected
`0`	End of packet condition not detected

Bit 23 – BSCLTO Bus SCL Time-out Flag bit

Value	Description
`1`	SCL Bus Time-out occurred
`0`	SCL Bus Time-out has not occurred

Bit 22 – HBCLTO Host Bus Cumulative Extended Time-out Flag bit

Value	Description
`1`	Host Bus Cumulative Extended Time-out occurred
`0`	Host Bus Cumulative Time-out has not occurred

Bit 21 – CBCLTO Client Bus Cumulative Extended Time-out Flag bit

Value	Description
`1`	Client Bus Cumulative Extended Time-out occurred
`0`	Client Bus Cumulative Extended Time-out has not occurred

Bit 20 – BITO Bus Idle Time-out Flag bit

Value	Description
`1`	Bus Idle Time-out occurred
`0`	Bus Idle Time-out has not occurred

Bit 19 – FRME Frame Error Detect Flag bit

Value	Description
`1`	Frame error detected in Client mode, STOP or START is received during the data byte transfer or data ACK transfer time
`0`	Frame error has not been detected in Client mode

Bit 18 – NACKE NACK Detect Error Flag bit

Value	Description
`1`	NACK detected as an Error
`0`	NACK has not been detected as an Error

Bit 16 – CRC CRC Error Flag bit

Value	Description
`1`	CRC Error occurred
`0`	CRC Error has not occurred

Bit 15 – STOPE Stop Condition Detect Event flag bit

Value	Description
`1`	Stop Condition detected
`0`	Stop Condition has not been detected

Bit 14 – STARTE Start Condition Detect Event Flag bit

Value	Description
`1`	Start Condition event detected
`0`	Start Condition event not detected

Bit 13 – HSTIF Host Detect Interrupt Flag bit

Value	Description
`1`	Host interrupt detected
`0`	Host interrupt not detected

Bit 12 – CLTIF Client Detect Interrupt Flag bit

Value	Description
`1`	Client interrupt detected
`0`	Client interrupt not detected

Bit 11 – ERR Error Detect Flag bit⁽⁴⁾

Value	Description
`1`	Error is detected
`0`	Error is not detected

Bits 3:0 – SCLCNT[3:0] SCL Count bits

Number of SCL clocks to be stored for Frame Error

20.4.11 I2Cx Status Register

Bit 31 – SSPND I2C Suspended bit