20.4.6 I²Cx Transmit Data Register

Table 20-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	I2CxTRN
Offset:	0x1894, 0x18E4


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	I2CTXDATA[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – I2CTXDATA[7:0] I²C Transmit Data Buffer bits

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20.4.6 I2Cx Transmit Data Register

Bits 7:0 – I2CTXDATA[7:0] I2C Transmit Data Buffer bits

20.4.6 I²Cx Transmit Data Register

Bits 7:0 – I2CTXDATA[7:0] I²C Transmit Data Buffer bits