20.4.10 I2Cx Interrupt Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | I2CxINTC |
| Offset: | 0x18A4, 0x18F4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| I2CEIE | CBCLIE | HPCIE | HSCIE | HBCLIE | EOPIE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BSCLTIE | HBCTIE | CBCTIE | BITIE | FRMEIE | NACKIE | CRCIE | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BCLDIE | HSBCLIE | HSTIE | CLTIE | HACKSIE | CADDRIE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXIE | TXIE | CDRXIE | CDTXIE | HDTXIE | HDRXIE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – I2CEIE Error Interrupt Enable bit
| Value | Description |
|---|---|
1 | Assert I2CIF if I2CEIF asserts. Merges error interrupts onto I2CIF. The ERR bit is not affected by setting this bit |
0 |
Disabled |
Bit 29 – CBCLIE Client Bus Collision Message Event Interrupt Enable bit (I2C Client mode only)
| Value | Description |
|---|---|
1 | Enable CLTIF interrupt on bus collision detect |
0 |
Bus collision interrupt is disabled |
Bit 28 – HPCIE Host STOP Condition Interrupt Enable bit
| Value | Description |
|---|---|
1 | Assert HSTIF when I2CxSTAT.P is set |
0 | Host STOP interrupt disabled |
Bit 27 – HSCIE Host START Condition Interrupt Enable bit
| Value | Description |
|---|---|
1 | Assert HSTIF when I2CxSTAT.S is set |
0 | Host START interrupt disabled |
Bit 26 – HBCLIE Host Bus Collision Message event Interrupt Enable bit (I2C Host mode only)
| Value | Description |
|---|---|
1 | Enable HSTIF interrupt on bus collision detect |
0 | Bus collision interrupt is disabled |
Bit 25 – EOPIE End of Packet Interrupt Enable bit
| Value | Description |
|---|---|
1 | End of packet interrupt is enabled |
0 | End of packet interrupt is disabled |
Bit 23 – BSCLTIE Bus SCL Low Time-out Enable bit
| Value | Description |
|---|---|
1 | Assert I2CEIF when I2CxSTAT2.BSCLTO is set |
0 | Bus SCL time-out not enabled |
Bit 22 – HBCTIE Host Bus Cumulative Time-out Interrupt Enable bit
| Value | Description |
|---|---|
1 | Assert I2CEIF when I2CxSTAT2.HBCLTO is set |
0 | Host bus cumulative time-out not enabled |
Bit 21 – CBCTIE Client Bus Cumulative Time-out Interrupt Enable bit
| Value | Description |
|---|---|
1 | Assert I2CEIF when I2CxSTAT2.CBCLTO is set |
0 | Client bus cumulative time-out not enabled |
Bit 20 – BITIE Bus Idle Time-out Enable Interrupt bit
| Value | Description |
|---|---|
1 | Assert I2CIF when I2CxSTAT2.BIT is set |
0 |
Bus free interrupt is disabled |
Bit 19 – FRMEIE Framing Error Detect Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Enable I2CEIF interrupt if FRME is set due to a framing error. A framing error occurs in Client mode if a STOP or START is received during the byte transfer time or ACK transfer time. |
0 | Frame error interrupt is disabled |
Bit 18 – NACKIE NACK Detect Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enable I2CEIF interrupt on NACK detect as an Error |
0 | NACK interrupt is disabled |
Bit 16 – CRCIE CRC Error Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enable I2CEIF interrupt on CRC error |
0 | CRC interrupts are disabled |
Bit 15 – BCLDIE Bus Collision Detect Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enable I2CEIF interrupt on bus collision |
0 | Bus collision interrupts are disabled |
Bit 14 – HSBCLIE Host Bus Collision Detect Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enable interrupt during the STOP sequence after receiving bus collision |
0 | An interrupt during the STOP sequence after receiving bus collision is disabled |
Bit 13 – HSTIE Host Interrupt Enable bit
| Value | Description |
|---|---|
1 | Assert I2CIF when I2CxSTAT2.HSTIFis set |
0 | Host interrupt is disabled |
Bit 12 – CLTIE Client Interrupt Enable bit
| Value | Description |
|---|---|
1 | Assert I2CIF when I2CxSTAT2.CLIIF is set |
0 | Client interrupt is disabled |
Bit 11 – HACKSIE Host ACK Sequence Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enable HSTIF interrupt on ACK sequence |
0 |
ACK sequence interrupt is disabled |
Bit 10 – CADDRIE Client Address Transaction Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enable CLTIF interrupt on address detect |
0 | Address detect interrupt is disabled |
Bit 7 – RXIE Receive Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enable the I2CRXIF interrupt when I2CxSTAT.RBF is set |
0 | Disable the I2CRXIF interrupt |
Bit 6 – TXIE Transmit Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enable the I2CTXIF interrupt when I2CxSTAT.TBF is cleared |
0 | Disable the I2CTXIF interrupt |
Bit 4 – CDRXIE Client Data Receive Buffer Full Interrupt Enable bit
| Value | Description |
|---|---|
1 | Include the I2CxSTAT.RBF=1 for the CLTIF interrupt |
0 | Exclude the I2CxSTAT.RBF=1 for the CLTIF interrupt |
Bit 3 – CDTXIE Host Data Transmit Buffer Empty Interrupt Enable bit
| Value | Description |
|---|---|
1 | Include the host I2CxSTAT.TBF=0 for the HSTIF interrupt |
0 | Exclude the I2CxSTAT.TBF=0 for the HSTIF interrupt |
Bit 1 – HDTXIE Host Data Transmit Buffer Empty Interrupt Enable bit
| Value | Description |
|---|---|
1 | Include the host I2CxSTAT.TBF=0 for the HSTIF interrupt |
0 | Exclude the I2CxSTAT.TBF=0 for the HSTIF interrupt |
Bit 0 – HDRXIE Host Data Receive Buffer Full Interrupt Enable bit
| Value | Description |
|---|---|
1 | Include the I2CxSTAT.RBF=1 for the HSTIF interrupt |
0 | Exclude the I2CxSTAT.RBF=1 for the HSTIF interrupt |