20.5.2.5.1 IWCOL Status Flag

If the user software writes to the I2CxTRN register when a receive is already in progress (that is, the I2CxRSR register is still shifting in a data byte), the IWCOL status bit (I2CxSTAT1[7]) is set and the contents of the buffer are unchanged (the write does not occur) (see Host Reception (7-bit Address) and Host Reception (10-bit Address)).

Note: Because queuing of events is not allowed, writing to the lower five bits of the I2CxCON1 register is disabled until the data reception condition is complete.

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