19.4.1.3.2 Enhanced Buffer Mode

The Enhanced Buffer Enable (ENHBUF) bit in the SPIx Control Register 1 (SPIxCON1[0]) can be set to enable the Enhanced Buffer mode.

In Enhanced Buffer mode, two FIFO buffers are used for the SPIx Transmit Buffer (SPIxTXB) and the SPIx Receive Buffer (SPIxRXB). SPIxBUF provides access to both the receive and transmit FIFOs. The data transmission and reception in the SPIxSR buffer is identical to that in the Standard Buffer mode. The FIFO depth depends on the data width chosen by the Word/Half-Word Byte Communication Select (MODE[32,16]) bits in the SPIx Control Register 1 (SPIxCON1[11:10]). The FIFO depth varies between devices. For a device with FIFO depth 'X', the MODE field will modify it as follows:

The SPITBF status bit is set when all of the elements in the transmit FIFO buffer are full, and it is cleared if one or more of those elements are empty. The SPIRBF status bit is set when all of the elements in the receive FIFO buffer are full, and it is cleared if the SPIxBUF buffer is read by the software.

The SPITBE status bit is set if all the elements in the transmit FIFO buffer are empty and is cleared otherwise. The SPIRBE bit is set if all of the elements in the receive FIFO buffer are empty and is cleared otherwise.

There is underrun or overflow protection against reading an empty receive FIFO element or writing a full transmit FIFO element. The SPIxSTAT register provides the SPIx Transmit Underrun bit (SPITUR) and the Receive Overflow Status bit (SPIROV). Depending on the requirements, IGNTUR and IGNROV can be configured for SPI operation to be continued or not at the time of error. When a Transmit Underrun occurs, the last received data or the data in the SPIxURDT register can be transmitted by configuring the URDTEN bit (SPIxCON1[26]).

The Receive Buffer Element Count bits (RXELM[2:0]) in the SPIx Status Register (SPIxSTAT[26:24]) indicate the number of unread elements in the receive FIFO. The Transmit Buffer Element Count bits (TXELM[2:0]) in the SPIx Status Register (SPIxSTAT[18:16]) indicate the number of elements not transmitted in the transmit FIFO.

When configured for non-framed Client mode, it is important to ensure that the software can reload the transmit buffer quickly enough to keep up with the configured transfer rate. If the SPIxTXB is empty at the start of a transaction, then the transmit behavior will be undefined and is likely to cause errors (duplicate transmissions, missed bits, etc.) in the received data.