12.4.2.1 Input Clock Limitation at Start-up for PLL Mode

Table 13-9 provides the default values of the PLL prescaler, PLL feedback divider and both PLL postscalers at Power-on Reset (POR).

Table 12-32. PLL Mode Defaults
RegisterBit FieldValue at POR ResetPLL Divider Ratio
PLLxDIVPLLPRE[3:0]0001N1 = 1
PLLxDIVPOSTDIV1[2:0]111N2 = 7
PLLxDIVPOSTDIV2[2:0]001N3 = 1
PLLxDIVPLLFBDIV[7:0]11001000M = 200

Given these Reset values, the following equations provide the PLL Input Frequency (FPLLI) and VCO Output Frequency (FVCO) at Power-on Reset.

Equation 12-4. FVCO at Power-on Reset
Equation 12-5. FPLLO at Power-on Reset

To use the PLL with settings other than the default settings and to ensure all PLL requirements are met, follow this process:

  1. Power up the device with the Internal FRC.
  2. Change the FBDIV, PLLPRE, POSTDIV1 and POSTDIV2 bit values, based on the input frequency, to meet these PLL requirements:

    The PLL Input Frequency (FPLLI) must be in the range specified in Electrical Characteristics.

    The VCO Output Frequency (FVCO) must be in the range specified in Electrical Characteristics.

  3. Writing PLLxCON:
    1. Enable PLL Input and Feedback Divider update by setting the PLLSWEN bit in the PLLxCON register.
    2. The first output divider (POSTDIV1) should be larger than the value for the second output divider (POSTDIV2). The output dividers POSTDIV1 and POSTDIV2 should not be changed while the PLL is operating. The input reference clock divider and the feedback divider may be updated during PLL operation.
    3. Enable PLL Output Divider update by setting the FOUTSWEN bit in the PLLxCON register.
    4. Select clock source by setting the NOSC[3:0] bits in the PLLxCON register.
    5. Enable clock switching by setting the OSWEN bit in the PLLxCON register.
      Note:
      1. It is recommended to change clock divider settings before the initial clock switch occurs. The reference clock (PLLPRE) and feedback dividers (FBDIV) can be changed during PLL operation, but care should be taken not to generate an invalid clock frequency.
      2. When switching from low-speed clock to a high-speed clock, the DIVSW process should be done before a clock switch to prevent undivided high speed clocks from passing through. For a high-to-low switch, the clock switch should occur before a DIVSW.