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High-Performance dsPIC33A Core with Floating-Point Unit, High-Speed ADCs and High-Resolution PWM

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12 Oscillator and Clocking Module
12.4 Operation
12.4.2 Phase-Locked Loop (PLL)
12.4.2.3 PLL Setup

dsPIC33AK128MC106 Product Family
Pin Diagrams
Pinout I/O Descriptions
Terminology Cross Reference
1 Device Overview
2 Guidelines for Getting Started with Digital Signal Controllers
3 CPU
4 Memory Organization
5 Data Memory
6 Flash Program Memory
7 Configuration Bits
8 Security Module
9 Resets
10 Interrupt Controller
11 I/O Ports with Edge Detect
12 Oscillator and Clocking Module
13 Direct Memory Access (DMA) Controller
14 High-Resolution Pulse-Width Modulation (PWM)
15 High-Speed, Low Latency ADC
16 High-Speed Analog Comparator with Slope Compensation DAC
17 Quadrature Encoder Interface (QEI)
18 Universal Asynchronous Receiver Transmitter (UART)
19 Serial Peripheral Interface (SPI)
20 Inter-Integrated Circuit (I²C)
21 Single-Edge Nibble Transmission (SENT)
22 Bidirectional Serial Synchronous (BiSS) Module
23 Timer1
24 Single-Output Capture/Compare/PWM/Timer Modules (SCCP)
25 Configurable Logic Cell (CLC)
26 Peripheral Trigger Generator (PTG)
27 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
28 Current Bias Generator (CBG)
29 Operational Amplifier (Op Amp)
30 Watchdog Timer (WDT)
31 Deadman Timer (DMT)
32 Device Power-Saving Modes
33 JTAG Interface
34 In-Circuit Debugger
35 Instruction Set Summary
36 Development Support
37 Electrical Characteristics
38 High-Temperature Electrical Characteristics
39 Packaging Information
40 Revision History
41 Product Identification System
Microchip Information

12.4.2.3 PLL Setup

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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