12.4.1.1 Fail-Safe Clock Monitor (FSCM)

Each CLKGEN has a FSCM built inside to provide clock safety. Each FSCM is enabled via CLKxCON.FSCMEN. To provide faster response to a clock failure, the FSCM uses the 8 MHz BFRC as the reference clock.

Note: FSCM supports automatic switchover to a backup clock source with options for programmable over-frequency or under-frequency thresholds.

In the event of an oscillator failure, the FSCM will generate an Oscillator Fail Interrupt, set the associated CLKFAIL/PLLFAIL flag, and switch the clock over to the specified backup Fail-Safe clock source, which is selected via CLKxCON.BOSC bits. The Fail-Safe condition is exited with either a Reset or by completing a clock switch to a new stable clock input for the CLKGEN.

Note: For CLKGEN1, select ONLY an active and running clock source as the BOSC source (such as FRC, BFRC, etc). At the time of BOSC initialization, the clock source should be up and running.

A clock monitor external to the CLKGENs is also included and is discussed in the Clock Monitor section.