12.4.1.2 Setup for Using Clock Generator with 8 MHz Internal FRC

The following process is used to set up the CLKGEN1 to operate the device with an 8 MHz Internal FRC:

To set up the fail-safe for the clock generator, follow these steps:
1. Select the backup clock source by selecting the BOSC bits in CLKxCON register.
2. Enable fail-safe clock failure by setting the FSCMEN bit in CLKxCON register.
3. Enable ClkFailInterrupt to generate an interrupt during clock failure.
To switch to a new oscillator for the clock generator, follow these steps:
1. Select clock source to switch by writing to NOSC bits in the CLKxCON register.
2. Enable switching by writing to the OSWEN bit in the CLKxCON register.
To further divide the clock out of the clock generator using CLKxDIV, follow these steps:
1. Set the integer divide factor bit setting INTDIV bits in the CLKxDIV register.
2. Set the fractional divide factor bit setting FRACDIV bits in the CLKxDIV register. FRACDIV will not work if INTDIV is configured to 0.
3. Set the DIVSWEN bit in the CLKxCON register to enable divide factors to get updated.
Enable the clock generator (if not enabled by default) by setting the ON bit in CLKxCON register.

Code Example for Clock Generator 1 Switching to FRC

//enable clock generator
    CLK1CONbits.ON = 1;
    CLK1CONbits.OE = 1;

    //configure backup oscillator in case of failure
    CLK1CONbits.BOSC = 2; //BFRC
    				//select backup clock source:
   				 //[1] = FRC - Internal 8 MHz RC oscillator
   				 //[2] = BFRC - Internal Backup 8 MHz RC oscillator
    				//[3] = POSC - Primary crystal oscillator (4-32 MHz)
    				//[4] = LPRC 
   				 //[5] = PLL1 Fout output
   				 //[6] = PLL2 Fout output
   				 //[7] = PLL1 VCO FracDiv output 
    				//[8] = PLL2 VCO FracDiv output 
    				//[9] = REFI1 - user definable clock source
    				//[10] = REFI2 - user definable clock source


    CLK1CONbits.FSCMEN = 1; //enable fail safe


    //configure clock divide
    CLK1DIVbits.INTDIV = 1; //integer divide factor
    CLK1DIVbits.FRACDIV = 0x0080; //fractional divide factor
    CLK1CONbits.DIVSWEN = 1; //enable divide factors to get updated
    while (CLK1CONbits.DIVSWEN); //hardware cleared 
    // Fdiv = Fin / 2*(INTDIV+(FRCDIV/512))

    //enable clock switching 
    CLK1CONbits.NOSC = 1 ; //select clock source
    			      //[1] = FRC - Internal 8 MHz RC oscillator
    			      //[2] = BFRC - Internal Backup 8 MHz RC oscillator
    			      //[3] = POSC - Primary crystal oscillator (4-32 MHz)
   			       //[4] = LPRC 
   			       //[5] = PLL1 Fout output
    			      //[6] = PLL2 Fout output
   			       //[7] = PLL1 VCO FracDiv output 
    			      //[8] = PLL2 VCO FracDiv output 
    			      //[9] = REFI1 - user definable clock source
    			     //[10] = REFI2 - user definable clock source

    CLK1CONbits.OSWEN = 1; //enable clock switching
    while (CLK1CONbits.OSWEN); //wait for switching(hardware clear))


    IFS0bits.CLKFAILIF = 0;    // enable clock failure interrupt
    IEC0bits.CLKFAILIE = 1;
}