36.7.16 Software Reset Register

Only part of a data circuit is reset. The DMA circuit is also reset.

The following registers and bits are cleared by this bit:

• Buffer Data Port Register BDPR: BUFDATA is cleared and initialized.
• Present State Register PSR36.7.9 Present State Register:
  • Buffer Read Enable (BUFRDEN)
  • Buffer Write Enable (BUFWREN)
  • Read Transfer Active (RTACT)
  • Write Transfer Active (WTACT)
  • DAT Line Active (DATLL)
  • Command Inhibit - DAT (CMDINHD)
• Block Gap Control Register BGCR:
  • Continue Request (CONTR)
  • Stop At Block Gap Request (STPBGR)
• Normal Interrupt Status Register NISTR36.7.17 Normal Interrupt Status Register:
  • Buffer Read Ready (BRDRDY)
  • Buffer Write Ready (BWRRDY)
  • DMA Interrupt (DMAINT)
  • Block Gap Event (BLKGE)
  • Transfer Complete (TRFC)

Only part of a command circuit is reset.

The following registers and bits are cleared by this bit:

• Present State Register PSR36.7.9 Present State Register:
  • Command Inhibit (CMD) (CMDINHC)
• Normal Interrupt Status Register NISTR36.7.17 Normal Interrupt Status Register:
  • Command Complete (CMDC)

This reset affects the entire peripheral except the card detection circuit. During initialization, the peripheral must be reset by setting this bit to 1. This bit is automatically cleared to 0 when CA0R and CA1R are valid and the user can read them. If this bit is set to 1, the user should issue a reset command and reinitialize the card.

List of registers cleared to 0:

• SDMA System Address / Argument 2 Register SSAR36.7.1 SDMA System Address / Argument 2 Register
• Block Size Register BSR
• Block Count Register BCR
• Argument 1 Register ARG1R
• Transfer Mode Register TMR
• Command Register CR
• Response Register n RR
• Buffer Data Port Register BDPR
• Present State Register PSR36.7.9 Present State Register (except CMDLL, DATLL, WRPPL, CARDDDPL, CARDSS, CARDINS)
• Host Control 1 Register HC1R36.7.10 Host Control 1 Register
• Power Control Register PCR
• Block Gap Control Register BGCR
• Wakeup Control Register WCR36.7.13 Wakeup Control Register: SD/SDIO
• Clock Control Register CCR36.7.14 Clock Control Register
• Timeout Control Register TCR36.7.15 Timeout Control Register
• Normal Interrupt Status Register NISTR36.7.17 Normal Interrupt Status Register
• Error Interrupt Status Register EISTR36.7.18 Error Interrupt Status Register
• Normal Interrupt Status Enable Register NISTER36.7.19 Normal Interrupt Status Enable Register: e.MMC
• Error Interrupt Status Enable Register EISTER36.7.20 Error Interrupt Status Enable Register
• Normal Interrupt Signal Enable Register NISIER36.7.21 Normal Interrupt Signal Enable Register
• Error Interrupt Signal Enable Register EISIER36.7.22 Error Interrupt Signal Enable Register
• Auto CMD Error Status Register ACESR
• Host Control 2 Register HC2R - DEFAULT
• ADMA Error Status Register AESR
• ADMA System Address Registers
• Slot Interrupt Status Register SISR
• e.MMC Control 1 Register MC1R
• e.MMC Control 2 Register MC2R
• AHB Control Register ACR
• Clock Control 2 Register CC2R
• Capabilities Control Register CACR (except KEY)