36.7.38 e.MMC Control 2 Register
| Name: | MC2R |
| Offset: | 0x205 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ABOOT | SRESP | ||||||||
| Access | W | W | |||||||
| Reset | 0 | 0 |
Bit 1 – ABOOT e.MMC Abort Boot
This bit is used to exit from Boot mode. Writing this bit to 1 exits the Boot Operation mode. Writing 0 is ignored.
Bit 0 – SRESP e.MMC Abort Wait IRQ
This bit is used to exit from the Interrupt mode. When this bit is written to 1, the peripheral sends the CMD40 response automatically. This brings the e.MMC from Interrupt mode to the standard Data Transfer mode. Writing this bit to 0 is ignored.
Note: This bit is only effective when CMD_TYP in MC1R is set to WAITIRQ.