36.7.22 Error Interrupt Signal Enable Register
Name: | EISIER |
Offset: | 0x3A |
Reset: | 0x0000 |
Property: | - |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
BOOTAE | ADMA | ACMD | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CURLIM | DATEND | DATCRC | DATTEO | CMDIDX | CMDEND | CMDCRC | CMDTEO | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 12 – BOOTAE Boot Acknowledge Error Signal Enable
Note: This register entry is specific to the e.MMC operation mode.
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.BOOTAE is set. |
1 | ENABLED | An interrupt is generated when EISTR.BOOTAE is set. |
Bit 9 – ADMA ADMA Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.ADMA is set. |
1 | ENABLED | An interrupt is generated when EISTR.ADMA is set. |
Bit 8 – ACMD Auto CMD Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.ACMD is set. |
1 | ENABLED | An interrupt is generated when EISTR.ACMD is set. |
Bit 7 – CURLIM Current Limit Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.CURLIM is set. |
1 | ENABLED | An interrupt is generated when EISTR.CURLIM is set. |
Bit 6 – DATEND Data End Bit Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.DATEND is set. |
1 | ENABLED | An interrupt is generated when EISTR.DATEND is set. |
Bit 5 – DATCRC Data CRC Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.DATCRC is set. |
1 | ENABLED | An interrupt is generated when EISTR.DATCRC is set. |
Bit 4 – DATTEO Data Timeout Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.DATTEO is set. |
1 | ENABLED | An interrupt is generated when EISTR.DATTEO is set. |
Bit 3 – CMDIDX Command Index Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.CMDIDX is set. |
1 | ENABLED | An interrupt is generated when EISTR.CMDIDX is set. |
Bit 2 – CMDEND Command End Bit Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.CMDEND is set. |
1 | ENABLED | An interrupt is generated when EISTR.CMDEND is set. |
Bit 1 – CMDCRC Command CRC Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.CMDCRC is set. |
1 | ENABLED | An interrupt is generated when EISTR.CMDCRC is set. |
Bit 0 – CMDTEO Command Timeout Error Signal Enable
Value | Name | Description |
---|---|---|
0 | MASKED | No interrupt is generated when EISTR.CMDTEO is set. |
1 | ENABLED | An interrupt is generated when EISTR.CMDTEO is set. |