36.7.27 Capabilities 1 Register
| Name: | CA1R |
| Offset: | 0x44 |
| Reset: | 0x00000070 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CLKMULT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TSDR50 | TCNTRT[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DRVDSUP | DRVCSUP | DRVASUP | DDR50SUP | SDR104SUP | SDR50SUP | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 23:16 – CLKMULT[7:0] Clock Multiplier
This field indicates the multiplier factor between the Base Clock (BASECLK) used for the Divided Clock Mode and the Multiplied Clock (MULTCLK) used for the Programmable Clock mode (refer to CCR).
Reading this field to 0 means that the Programmable Clock mode is not supported.
Bit 13 – TSDR50 Use Tuning for SDR50
If this bit is set to 1, the peripheral requires tuning to operate SDR50 (tuning is always required to operate SDR104).
| Value | Description |
|---|---|
| 0 |
SDR50 does not require tuning. |
| 1 |
SDR50 requires tuning. |
Bits 11:8 – TCNTRT[3:0] Timer Count For Re-Tuning
This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode (RTMODE) 1 to 3. Reading this field at 0 means that the Re-Tuning Timer is disabled. The Re-Tuning Timer initial value ranges from 0 to 1024 seconds.
Bit 6 – DRVDSUP Driver Type D Support
| Value | Description |
|---|---|
| 0 | Driver type D is not supported. |
Bit 5 – DRVCSUP Driver Type C Support
| Value | Description |
|---|---|
| 0 | Driver type C is not supported. |
Bit 4 – DRVASUP Driver Type A Support
| Value | Description |
|---|---|
| 0 | Driver type A is not supported. |
Bit 2 – DDR50SUP DDR50 Support
| Value | Description |
|---|---|
| 0 | DDR50 mode is not supported. |
Bit 1 – SDR104SUP SDR104 Support
| Value | Description |
|---|---|
| 0 | SDR104 mode is not supported. |
| 1 | SDR104 mode is supported. |
Bit 0 – SDR50SUP SDR50 Support
| Value | Description |
|---|---|
| 0 | SDR50 mode is not supported. |
| 1 | SDR50 mode is supported. |