1.7.4 Simulating the Design

The pattern generator module generates a counter/prbs-31 pattern used to drive the transceiver in 64b66b mode, and the pattern checker checks the packet and generator error flags.

  1. Open Libero SoC design built through the TCL scripts.
  2. To run the simulation, navigate to Stimulus Hierarchy, right-click the top.v file, and select Set as active stimulus.
  3. In the Design Flow tab, double-click Simulate under Verify Pre-Synthesized Design to simulate the design, as shown in the following figure.
    Figure 1-18. Simulation in Design Flow