1.7.5 Simulation Flow

The following steps describe the simulation flow:
  1. Initially, the transceiver is at reset.
  2. The pattern generator sends 64b66b start of sequence ("78 00 00 00 00 00 00 00") using sync header "10".
  3. Once the lane_status_lock is asserted and transceiver is ready, the pattern generator sends counter pattern using the sync header "01".
  4. Transmitter lanes are connected to receiver lanes internally in the testbench stimulus.
  5. The pattern checker waits for the valid data and starts checking the received data.

The following figures show the simulation waveform for the 64b66b design highlighting pattern checker status signals and Tx/Rx data match. The simulation run time will be 78 us approximately.

Figure 1-19. Simulation Waveform for 64b66b Design Highlighting Pattern Checker Status
Figure 1-20. Simulation Waveform for 64b66b Design Highlighting Tx and Rx Data Match