1.7.3 Port Description

The following table lists the important ports for the design.

Table 1-5. Port List for the 64b66b Design
PortDirectionDescription
LANE0_RXD_PInputTransceiver receiver differential input
LANE0_RXD_NInputTransceiver receiver differential input
REF_CLK_PAD_PInputTransmit PLL input clock from reference clock interface
REF_CLK_PAD_NInputTransmit PLL input clock from reference clock interface
LANE0_PCS_ARST_NInputAsynchronous active-low reset for the PCS logic
LANE0_PMA_ARST_NInputAsynchronous active-low reset for the PMA logic
reset_nInputActive low reset for the fabric logic
clr_err_counterInputError counter clear input
LANE0_TXD_POutputTransceiver transmitter differential output
LANE0_TXD_NOutputTransceiver transmitter differential output
LANE0_STATUS_LOCKOutputIndicates the lane status
LANE0_RX_VALOutputReceives data valid flag associated with a lane
error_out_oOutputError Flags
error_count_o[31:0]OutputError count Flags
Lock_oOutputData lock flag