21.3.5 SMTxCON0
SMT Control Register 0
| Name: | SMTxCON0 |
| Offset: | 0x0498 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN | STP | WPOL | SPOL | CPOL | PS[1:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – EN SMT Enable bit
| Value | Description |
|---|---|
1 |
SMT is enabled |
0 |
SMT is disabled; internal states are reset, clock requests are disabled |
Bit 5 – STP SMT Counter Halt Enable bit
| Value | Name | Description |
|---|---|---|
1 |
When SMTxTMR = SMTxPR |
Counter remains SMTxPR; period match interrupt occurs when clocked |
0 |
When SMTxTMR = SMTxPR |
Counter resets to 0x000000; period match interrupt occurs when clocked |
Bit 4 – WPOL SMTxWIN Input Polarity Control bit
| Value | Description |
|---|---|
1 |
Window signal is active-low/falling edge enabled |
0 |
Window signal is active-high/rising edge enabled |
Bit 3 – SPOL SMTxSIG Input Polarity Control bit
| Value | Description |
|---|---|
1 |
SMT Signal is active-low/falling edge enabled |
0 |
SMT Signal is active-high/rising edge enabled |
Bit 2 – CPOL SMT Clock Input Polarity Control bit
| Value | Description |
|---|---|
1 |
SMTxTMR increments on the falling edge of the selected clock signal |
0 |
SMTxTMR increments on the rising edge of the selected clock signal |
Bits 1:0 – PS[1:0] SMT Prescale Select bits
| Value | Description |
|---|---|
11 |
Prescaler = 1:8 |
10 |
Prescaler = 1:4 |
01 |
Prescaler = 1:2 |
00 |
Prescaler = 1:1 |