PIC16(L)F18425/45

21.1.6.3 Period and Duty Cycle Measurement Mode

In this mode, either the duty cycle or period (depending on polarity) of the input signal can be acquired relative to the SMT clock. The CPW register is updated on a falling edge of the signal, and the CPR register is updated on a rising edge of the signal, along with the SMTxTMR resetting to 0x000001. In addition, the SMTxGO bit is reset on a rising edge when the SMT is in Single Acquisition mode. See the figures below.

Figure 21-5. Period and Duty Cycle, Repeat Acquisition Mode Timing Diagram

Figure 21-6. Period and Duty Cycle, Single Acquisition Mode Timing Diagram

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