PIC16(L)F18425/45

21.1.6.2 Gated Timer Mode

Gated Timer mode uses the signal input (SSEL) to control whether or not the SMTxTMR will increment. Upon a falling edge of the signal, the SMTxCPW register will update to the current value of the SMTxTMR. Example waveforms for both repeated and single acquisitions are provided in figures below.

Figure 21-3. Gated Timer Mode, Repeat Acquisition Timing Diagram

Figure 21-4. Gated Timer Mode, Single Acquisition Timing Diagram

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.