36.14.19 PHY Control Register 50

Note: The USB PHY values must be loaded from the CAL OTP area into the USB PHY registers by software, before enabling the USB, to achieve the specified accuracy.

Table 36-109. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PHY50
Offset:	0x1550
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	COMPCURREF[2:0]				ASESSVALIDTUNE[2:0]			BSESSVALIDTUNE
Access	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Reset	0	0	0		0	0	0	0

Bits 7:5 – COMPCURREF[2:0] Compensation Current Tuning Reference

Value	Description
111	162.5 mV
110	175 mV
101	212.5 mV
100	250 mV
011	237.5 mV
010	225 mV
001	187.5 mV
000	200 mV

Bits 3:1 – ASESSVALIDTUNE[2:0] A Session Valid Reference Tune

Value	Description
111	1.2 V
110	1.55 V
101	1.5 V
100	1.45 V
011	1.25 V
010	1.3 V
001	1.35 V
000	1.4 V (Default)

Bit 0 – BSESSVALIDTUNE B Session Valid Reference Tune

Settings include the lower bits (PHY4C.6:7) and the upper bit (PHY50.0).

Value	Description
111	2.16 V
110	2.58 V
101	2.52 V
100	2.46 V
011	2.22 V
010	2.28 V
001	2.34 V
000	2.4 V (Default)

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