36.14.9 PHY Control Register 10
Note: The USB PHY values must be loaded from the CAL OTP area into
the USB PHY registers by software, before enabling the USB, to achieve the specified
accuracy.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PHY10 |
| Offset: | 0x1510 |
| Reset: | 0x000000AA |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DRVTUNE[2:0] | TUNE[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | |
Bits 7:5 – DRVTUNE[2:0] Driver Strength Tuning
Sets the lower 3 bits for the HS/FS/LS driver strength tuning.
Settings include the lower bits (PHY10.5:7) and the upper bit (PHY14.0:1).
| Value | Description |
|---|---|
| 11111 | Fastest rise fall time |
| 00000 | Slowest rise fall time |
Bits 4:0 – TUNE[4:0] Amplitude Tuning
Sets the upper 5 bits of the HS amplitude tuning.
Settings include the lower bits (PHY0C.5:7) and the upper bit the upper bit (PHY10.0:4) – setting of each bit location lowers the amplitude by the same amount regardless of location.
| Value | Description |
|---|---|
| 11111111 | Setting with the smallest amplitude |
| 10101100 | 4-‘0’ and 4-‘1’ is the middle amplitude |
| 00000000 | Setting with the largest amplitude |