36.14.2 TX Control Status Register High for Endpoint 1-7

Table 36-92. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: TXCSRH
Offset: 0x1013
Reset: 0x0000
Property: PAC Write-Protection

Bit 76543210 
 AUTOSETISOMODEDMAREQENFRCDATATOGDMAREQMODE   
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 7 – AUTOSET Auto Set Control bit

ValueDescription
0 TXPKTRDY must be set manually for all packet sizes
1 TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TXPKTRDY will have to be set manually.

Bit 6 – ISO Isochronous TX Endpoint Enable bit

This bit only has an effect in Device mode. In Host mode, it always returns zero.

ValueDescription
0 Disables the endpoint for Isochronous transfers and enables it for Bulk or Interrupt transfers.
1 Enables the endpoint for Isochronous transfers

Bit 5 – MODE Endpoint Direction Control bit

This bit only has any effect where the same endpoint FIFO is used for both TX and RX transactions.

ValueDescription
0 Endpoint is RX
1 Endpoint is TX

Bit 4 – DMAREQEN Endpoint DMA Request Enable bit

ValueDescription
0 DMA requests are disabled for this endpoint
1 DMA requests are enabled for this endpoint

Bit 3 – FRCDATATOG Force Endpoint Data Toggle Control bit

ValueDescription
0 No forced behavior
1 Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received.

Bit 2 – DMAREQMODE Endpoint DMA Request Mode Control bit

This bit must not be cleared either before or in the same cycle as the DMAREQEN bit is cleared.

ValueDescription
0 DMA Request Mode0
1 DMA Request Mode1