36.14.10 PHY Control Register 14

Note: The USB PHY values must be loaded from the CAL OTP area into the USB PHY registers by software, before enabling the USB, to achieve the specified accuracy.

Table 36-100. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PHY14
Offset:	0x1514
Reset:	0x00000012
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	ODT			BYPSSSQUELCH		COMPBYPSS[2:0]
Access	R/W			R/W		R/W	R/W	R/W
Reset	0			1		0	0	0

Bit 7 – ODT On Die Termination

Sets the lowest bit of the on die termination compensation voltage reference.

Settings include the lower bits (PHY14.8) and the upper bit the upper bits (PHY18.0:1).

Value	Description
111	362.5 mV
110	375 mV
101	387.5 mV
100	450 mV
011	437.5 mV
010	425 mV
001	412.5 mV
000	400 mV

Bit 4 – BYPSSSQUELCH Bypass Squelch Trigger Point

Sets the bypass squelch trigger point configure in chirp mode.

Value	Description
1	Bypass
0	Do not bypass

Bits 2:0 – COMPBYPSS[2:0] Auto-Compression Bypass

Sets the auto-compression bypass.

Settings include the lower bits (PHY0C.5:7) and the upper bit the upper bit (PHY10.0:4) – setting of each bit location lowers the amplitude by the same amount regardless of location.

Value	Description
11	Disable current and disable ODT auto-calibration
10	Disable current and enable ODT auto-calibration
01	Enable current and disable ODT auto-calibration
00	Enable current and ODT auto-calibration

Bits 1:0 – DRVTUNE[1:0] HS/FS/LS Driver Strength Tuning

Sets the upper 2 bits for HS/FS/LS driver strength tuning.

Settings include the lower bits (PHY10.5:7) and the upper bit (PHY14.0:1).

Value	Description
11111	Fastest rise fall time
00000	Slowest rise fall time