36.14.16 PHY Control Register 44
Note: The USB PHY values must be loaded from the CAL OTP area into
the USB PHY registers by software, before enabling the USB, to achieve the specified
accuracy.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PHY44 |
| Offset: | 0x1544 |
| Reset: | 0x00000040 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FRCSESSEND | FRCVBUSVAL | DIGDBG | PLLDAMP | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – FRCSESSEND Force Session End
| Value | Description |
|---|---|
| 1 | - |
| 0 | Default |
Bit 3 – FRCVBUSVAL Force Output VBUS_VALID
| Value | Description |
|---|---|
| 1 | - |
| 0 | Default |
Bit 2 – DIGDBG Digital Debug Interface (Reserved)
| Value | Description |
|---|---|
| 1 | - |
| 0 | Default |
Bit 1 – PLLDAMP Digital Debug Interface (Reserved)
| Value | Description |
|---|---|
| 1 | Decreased PLL damping factor |
| 0 | Increased PLL damping factor (default) |