36.14.15 PHY Control Register 28
Note: The USB PHY values must be loaded from the CAL OTP area into
the USB PHY registers by software, before enabling the USB, to achieve the specified
accuracy.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PHY28 |
| Offset: | 0x1528 |
| Reset: | 0x0000001B |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HSDRVCOMP[2:0] | DISCONDET[3:0] | HSDRIVST | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | |
Bits 7:5 – HSDRVCOMP[2:0] HS Driver Current Compensation
Sets the HS driver current compensation voltage reference.
| Value | Description |
|---|---|
| 111 | 362.5 mV |
| 110 | 375 mV |
| 101 | 387.5 mV |
| 100 | 450 mV |
| 011 | 437.5 mV |
| 010 | 425 mV |
| 001 | 412.5 mV |
| 000 | 400 mV |
Bits 4:1 – DISCONDET[3:0] HOST Disconnect Detection
Sets the HOST disconnect detection trigger point.
| Value | Description |
|---|---|
| 1111 | Reserved |
| 1110 | 612.5 mV |
| 1101 | 650 mV |
| 1100 | Reserved |
| 1011 | Reserved |
| 1010 | 58705 mV |
| 1001 | Reserved |
| 1000 | 600 mV |
| 0111 | Reserved |
| 0110 | 537.5 mV |
| 0101 | Reserved |
| 0100 | 550 mV |
| 0011 | 625 mV |
| 0010 | 562.5 mV |
| 0001 | 600 mV |
| 0000 | 575 mV |
Bit 0 – HSDRIVST HS Transmit Driver Strength
Sets the HS transmit driver strength.
Settings include the lower bits (PHY24.6:7) and the upper bit (PHY28.0).
| Value | Description |
|---|---|
| 111 | Strongest drive strength |
| 000 | Weakest drive strength |