35.6.27 SQI INTERRUPT SIGNAL ENABLE REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTSIGEN |
| Offset: | 0x158 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DMAEISE | PKTDONEISE | BDDONEISE | CONTHRISE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CONEMPTYISE | CONFULLISE | RXTHRISE | RXFULLISE | RXEMPTYISE | TXTHRISE | TXFULLISE | TXEMPTYISE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 11 – DMAEISE DMA Bus Error Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 10 – PKTDONEISE Receive Error Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 9 – BDDONEISE Transmit Error Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 8 – CONTHRISE Control Buffer Threshold Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 7 – CONEMPTYISE Control Buffer Empty Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 6 – CONFULLISE Control Buffer Full Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 5 – RXTHRISE Receive Buffer Threshold Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 4 – RXFULLISE Receive Buffer Full Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 3 – RXEMPTYISE Receive Buffer Empty Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 2 – TXTHRISE Transmit Buffer Threshold Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 1 – TXFULLISE Transmit Buffer Full Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |
Bit 0 – TXEMPTYISE Transmit Buffer Empty Interrupt Signal Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt signal is enabled |
| 0 | Interrupt signal is disabled |