35.6.6 SQI XIP CONTROL REGISTER 1

Table 35-6. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	XCON1
Offset:	0x100
Reset:	0x0000


Bit	31	30	29	28	27	26	25	24
			SDRCMD	DDRDATA	DDRDUMMY	DDRMODE	DDRADDR	DDRCMD
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DUMMYBYTES[2:0]			ADDRBYTES[2:0]			READOPCODE[7:6]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	READOPCODE[5:0]						TYPEDATA[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TYPEDUMMY[1:0]		TYPEMODE[1:0]		TYPEADDR[1:0]		TYPECMD[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 29 – SDRCMD SQI Command in SDR Mode bit

Value	Description
1	SQI command is in SDR mode and SQI data is in DDR mode
0	SQI command is in DDR mode and SQI data is in DDR mode

Bit 28 – DDRDATA SQI Data DDR Mode bit

Value	Description
1	SQI data bytes are transferred in DDR mode
0	SQI data bytes are transferred in SDR mode

Bit 27 – DDRDUMMY SQI Dummy DDR Mode bit

Value	Description
1	SQI dummy bytes are transferred in DDR mode
0	SQI dummy bytes are transferred in SDR mode

Bit 26 – DDRMODE SQI DDR Mode bit

Value	Description
1	SQI mode bytes are transferred in DDR mode
0	SQI mode bytes are transferred in SDR mode

Bit 25 – DDRADDR SQI Address Mode bit

Value	Description
1	SQI address bytes are transferred in DDR mode
0	SQI address bytes are transferred in SDR mode

Bit 24 – DDRCMD SQI DDR Command Mode bit

Note: When DDRCMD is set to '0', the SQI module will ignore the value in the SDRCMD bit.

Value	Description
1	SQI command bytes are transferred in DDR mode
0	SQI command bytes are transferred in SDR mode

Bits 23:21 – DUMMYBYTES[2:0] Transmit Dummy Bytes bits <2:0>

Value	Description
111	Transmit seven dummy bytes after the address bytes
011	Transmit three dummy bytes after the address bytes
010	Transmit two dummy bytes after the address bytes
001	Transmit one dummy bytes after the address bytes
000	Transmit zero dummy bytes after the address bytes

Bits 20:18 – ADDRBYTES[2:0] Address Cycle bits <2:0>

Value	Description
111	Reserved
101	Reserved
100	Four address bytes
011	Three address bytes
010	Two address bytes
001	One address bytes
000	Zero address bytes

Bits 17:10 – READOPCODE[7:0] Op code Value for Read Operation bits <7:0>

Bits 9:8 – TYPEDATA[1:0] SQI Type Data Enable bits <1:0>

Value	Description
11	Reserved
10	Quad Lane mode data is enabled
01	Dual Lane mode data is enabled
00	Single Lane mode data is enabled

Bits 7:6 – TYPEDUMMY[1:0] SQI Type Dummy Enable bits <1:0>

Value	Description
11	Reserved
10	Quad Lane mode dummy is enabled
01	Dual Lane mode dummy is enabled
00	Single Lane mode dummy is enabled

Bits 5:4 – TYPEMODE[1:0] SQI Type Mode Enable bits <1:0>

Value	Description
11	Reserved
10	Quad Lane mode is enabled
01	Dual Lane mode is enabled
00	Single Lane mode is enabled

Bits 3:2 – TYPEADDR[1:0] SQI Type Address Enable bits <1:0>

Value	Description
11	Reserved
10	Quad Lane mode address is enabled
01	Dual Lane mode address is enabled
00	Single Lane mode address is enabled

Bits 1:0 – TYPECMD[1:0] SQI Type Command Enable bits <1:0>

Value	Description
11	Reserved
10	Quad Lane mode command is enabled
01	Dual Lane mode command is enabled
00	Single Lane mode command is enabled

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.