35.6.31 SQI XIP CONTROL REGISTER 4

Table 35-31. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	XCON4
Offset:	0x168
Reset:	0x0000
Property:	-


Bit	31	30	29	28	27	26	25	24
				INIT2SCHECK	INIT2COUNT[1:0]		INIT2TYPE[1:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	INIT2CMD3[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	INIT2CMD2[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	INIT2CMD1[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 28 – INIT2SCHECK Flash Initialization 2 Command Status Check bit

Value	Description
1	Check the status after executing the INIT2 commands
0	Do not check the status

Bits 27:26 – INIT2COUNT[1:0] Flash Initialization 2 Command Count bits <1:0>

Value	Description
11	INIT2CMD1, INIT2CMD2, and INIT2CMD3 are sent
10	INIT2CMD1 and INIT2CMD2 are sent, but INIT2CMD3 is still pending
01	INIT2CMD1 is sent, but INIT2CMD2 and INIT2CMD3 are still pending
00	No commands are sent

Bits 25:24 – INIT2TYPE[1:0] Flash Initialization 2 Command Type bits <1:0>

Value	Description
11	Reserved
10	INIT2 commands are sent in Quad Lane mode
01	INIT2 commands are sent in Dual Lane mode
00	INIT2 commands are sent in Single Lane mode

Bits 24:16 – INIT2CMD3[8:0] Flash Initialization Command 3 bits <7:0>

Third command of the Flash initialization.

Bits 15:8 – INIT2CMD2[7:0] Flash Initialization Command 2 bits <7:0>

Second command of the Flash initialization.

Bits 7:0 – INIT2CMD1[7:0] Flash Initialization Command 1 bits <7:0>

First command of the Flash initialization

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