35.6.3 Interrupt Enable Set Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENSET |
| Offset: | 0x014 |
| Reset: | 0x000 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SQI | |||||||||
| Access | R/S | ||||||||
| Reset | 0 |
Bit 0 – SQI SQI Interrupt Enable Set
Writing a ‘1’ to this field clears the interrupt enable.
When read, the value return reflects the state of the enable as denoted below.
| Value | Description |
|---|---|
| 0 | Interrupt disabled |
| 1 | Interrupt enabled |