35.6.18 SQI STATUS REGISTER 2

Table 35-18. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit
Name: STAT2
Offset: 0x130
Reset: 0x0000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       CMDSTAT[1:0] 
Access RR 
Reset 00 
Bit 15141312111098 
      CONAVAIL[3:1] 
Access RRR 
Reset 000 
Bit 76543210 
 CONAVAIL[0]SQID3SQID2SQID1SQID0 RXUNTXOV 
Access RRRRRRR 
Reset 0000000 

Bits 17:16 – CMDSTAT[1:0] Current Command Status bits <1:0>

These bits indicate the current command status.

ValueDescription
11 Reserved
10 Receive
01 Transmit
00 Idle

Bits 10:7 – CONAVAIL[3:0] Control buffer Space Available bits <3:0>

These bits indicate the available control wordspace.

ValueDescription
1000 8 words are available
0111 7 words are available
0001 1 word is available
0000 No words are available

Bit 6 – SQID3 SQID3 Status bit

ValueDescription
1 Data is present on SQID3
0 Data is not present on SQID3

Bit 5 – SQID2 SQID2 Status bit

ValueDescription
1 Data is present on SQID2
0 Data is not present on SQID2

Bit 4 – SQID1 SQID1 Status bit

ValueDescription
1 Data is present on SQID1
0 Data is not present on SQID1

Bit 3 – SQID0 SQID0 Status bit

ValueDescription
1 Data is present on SQID0
0 Data is not present on SQID0

Bit 1 – RXUN Receive buffer Underflow Status bit

ValueDescription
1 Receive buffer Underflow has occurred
0 Receive buffer underflow has not occurred

Bit 0 – TXOV Transmit buffer Overflow Status bit

ValueDescription
1 Transmit buffer overflow has occurred
0 Transmit buffer overflow has not occurred