35.6.9 SQI CONTROL REGISTER

If it is Transmit, commands are initiated based on a write to the transmit register or the contents of TX buffer. If CMDINIT is Receive, commands are initiated based on reads to the read register or RX buffer availability.

These bits specify the total number of bytes to transmit or received (based on CMDINIT).

Table 35-9. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CON
Offset:	0x10C
Reset:	0x0000
Property:	-


Bit	31	30	29	28	27	26	25	24
							Reserved	SCHECK
Access							R	RW
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	DDRMODE	DASSERT	DEVSEL[1:0]		LANEMODE[1:0]		CMDINIT[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TXRXCOUNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TXRXCOUNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 25 – Reserved

Must be programmed as ‘0’

Bit 24 – SCHECK Flash Status Check bit

Note: When this bit is set to '1', the SQI module uses the MEMSTAT register to control the status check command process.

Value	Description
1	Check the status of the Flash
0	Do not check the status of the Flash

Bit 23 – DDRMODE Double Data Rate Mode bit

Value	Description
1	Set the SQI transfers to DDR mode
0	Set the SQI transfers to SDR mode

Bit 22 – DASSERT Chip Select Assert bit

Value	Description
1	Chip Select is deasserted after transmission or reception of the specified number of bytes
0	Chip Select is not deasserted after transmission or reception of the specified number of bytes

Bits 21:20 – DEVSEL[1:0] SQI Device Select bits <1:0>

Value	Description
11	Reserved
10	Reserved
01	Select Device 1
00	Select Device 0

Bits 19:18 – LANEMODE[1:0] SQI Lane Mode Select bits <1:0>

Value	Description
11	Reserved
10	Quad Lane mode
01	Dual Lane mode
00	Single Lane mode

Bits 17:16 – CMDINIT[1:0] Command Initiation Mode Select bits <1:0>

If it is Transmit, commands are initiated based on a write to the transmit register or the contents of Tx buffer. If CMDINIT is Receive, commands are initiated based on reads to the read register or Rx buffer availability.

Value	Description
11	Reserved
10	Receive
01	Transmit
00	Idle

Bits 15:0 – TXRXCOUNT[15:0] Transmit/Receive Count bits <15:0>

These bits specify the total number of bytes to transmit or received (based on CMDINIT).