Jump to main content
35.6.7 SQI XIP CONTROL REGISTER 2 These bits contain the 8-bit code value for the mode bits.
Table 35-7. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R Readable bit
HC Cleared by Hardware
(Grey cell)
Unimplemented
W Writable bit
HS Set by Hardware
X Bit is unknown at Reset
K Write to clear
S Software settable bit
—
—
Name: XCON2 Offset: 0x104 Reset: 0x0000
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 DEVSEL[1:0] MODEBYTES[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0 MODECODE[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 11:10 – DEVSEL[1:0] Device Select bits
<1:0>
Value Description
11
Reserved
10
Reserved
01
Device 1 is
selected
00
Device 0 is
selected
Bits 9:8 – MODEBYTES[1:0] Mode Byte Cycle Enable bits
<1:0>
Value Description
11
Three
cycles
10
Two
cycles
01
One
cycle
00
Zero
cycles
Bits 7:0 – MODECODE[7:0] Mode Code Value bits
<7:0>
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
