35.6.10 SQI CLOCK CONTROL REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CLKCON |
| Offset: | 0x110 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CLKDIV[10:8] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CLKDIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STABLE | EN | ||||||||
| Access | R | R/W | |||||||
| Reset | 0 | 0 |
Bits 18:8 – CLKDIV[10:0] SQI Clock Tsqi Frequency Select bit <10:0>
Note: Refer to the Electrical Characteristics for the maximum clock frequency
specifications.
Setting these bits to ‘00000000’ specifies the highest frequency of the SQI clock.
| Value | Description |
|---|---|
| 10000000000 | Base clock Tbc is divided by 2048 |
| 01000000000 | Base clock Tbc is divided by 1024 |
| 00100000000 | Base clock Tbc is divided by 512 |
| 00010000000 | Base clock Tbc is divided by 256 |
| 00001000000 | Base clock Tbc is divided by 128 |
| 00000100000 | Base clock Tbc is divided by 64 |
| 00000010000 | Base clock Tbc is divided by 32 |
| 00000001000 | Base clock Tbc is divided by 16 |
| 00000000100 | Base clock Tbc is divided by 8 |
| 00000000010 | Base clock Tbc is divided by 4 |
| 00000000001 | Base clock Tbc is divided by 2 |
| 00000000000 | Base clock Tbc |
Bit 1 – STABLE Tsqi Clock Stable Select bit
This bit is set to '1' when the SQI clock, TSQI, is stable after
writing a '1' to the EN bit.
| Value | Description |
|---|---|
| 1 | Tsqi clock is stable |
| 0 | Tsqi clock is not stable |
Bit 0 – EN Tsqi Clock Enable Select bit
When clock oscillation is stable, the SQI module will set the STABLE bit to
'1'.
| Value | Description |
|---|---|
| 1 | Enable the SQI clock (Tsqi) (when clock oscillation is stable, the SQI module sets the STABLE bit to ‘1’) |
| 0 | Disable the SQI clock (Tsqi) (the SQI module should stop its clock to enter a low power state); SFRs can still be accessed, as they use PBCLK5 |