35.6.8 SQI CONFIGURATION REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CFG |
| Offset: | 0x108 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CSEN[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SQIEN | DATAEN[1:0] | CONBUFRST | RXBUFRST | TXBUFRST | RESET | ||||
| Access | R/W | R/W | R/W | R/W/HC | R/W/HC | R/W/HC | R/W/HC | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Reserved[1:0] | BURSTEN | Reserved | HOLD | WP | Reserved[2] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved[1:0] | LSBF | CPOL | CPHA | MODE[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 27:24 – CSEN[3:0] Chip Select Output Enable bits <1:0>
| Value | Description |
|---|---|
| 1111 | Chip Select 3, 2, 1 and 0 are used |
| 1110 | Chip Select 3, 2 and 1 are used |
| 1101 | Chip Select 3, 2 and 0 are used |
| 1100 | Chip Select 3 and 2 are used |
| 1011 | Chip Select 3, 1 and 0 are used |
| 1010 | Chip Select 3 and 1 are used |
| 1001 | Chip Select 3 and 0 are used |
| 1000 | Chip Select 3 is used |
| 0111 | Chip Select 2, 1 and 0 are used |
| 0110 | Chip Select 2 and 1 are used |
| 0101 | Chip Select 2 and 0 are used |
| 0100 | Chip Select 2 is used |
| 0011 | Chip Select 1 and 0 are used |
| 0010 | Chip Select 1 is used |
| 0001 | Chip Select 0 is used |
| 0000 | No chip is selected |
Bit 23 – SQIEN SQI Enable bit
| Value | Description |
|---|---|
| 1 | SQI module is enabled |
| 0 | SQI module is disabled |
Bits 21:20 – DATAEN[1:0] Data Output Enable bits <1:0>
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | SQID3-SQID0 outputs are enabled |
| 01 | SQID1 and SQID0 data outputs are enabled |
| 00 | SQID0 data output is enabled |
Bit 19 – CONBUFRST Control Buffer Reset bit
| Value | Description |
|---|---|
| 1 | A reset pulse is generated clearing the control buffer |
| 0 | A reset pulse is not generated |
Bit 18 – RXBUFRST Receive Buffer Reset bit
| Value | Description |
|---|---|
| 1 | A reset pulse is generated clearing the receive buffer |
| 0 | A reset pulse is not generated |
Bit 17 – TXBUFRST Transmit Buffer Reset bit
| Value | Description |
|---|---|
| 1 | A reset pulse is generated clearing the transmit buffer |
| 0 | A reset pulse is not generated |
Bit 16 – RESET Software Reset Select bit
| Value | Description |
|---|---|
| 1 | A reset pulse is generated |
| 0 | A reset pulse is not generated |
Bits 14:13 – Reserved[1:0]
Must be programmed as ‘0’
Bit 12 – BURSTEN Burst Configuration bit
Note: This bit must be programmed as'
1'.| Value | Description |
|---|---|
| 1 | Burst is enabled |
| 0 | Burst is not enabled |
Bit 11 – Reserved
Must be programmed as ‘0’
Bit 10 – HOLD Hold bit
In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is connected.
Bit 9 – WP Write Protect bit
In Single Lane or Dual Lane mode, this bit is used to drive the SQID2 pin, which can be used with devices with a write-protect pin. The meaning of the values for this bit will depend on the device to which SQID2 is connected.
Bits 8:6 – Reserved[2:0]
Must be programmed as ‘0’
Bit 5 – LSBF Data Format Select bit
| Value | Description |
|---|---|
| 1 | LSB is sent or received first |
| 0 | MSB is sent or received first |
Bit 4 – CPOL Clock Polarity Select bit
| Value | Description |
|---|---|
| 1 | Active-low SQICLK (SQICLK high is the Idle state) |
| 0 | Active-high SQICLK (SQICLK low is the Idle state) |
Bit 3 – CPHA Clock Phase Select bit
| Value | Description |
|---|---|
| 1 | SQICLK starts toggling at the start of the first data bit |
| 0 | SQICLK starts toggling at the middle of the first data bit |
Bits 2:0 – MODE[2:0] Mode Select bits <2:0>
| Value | Description |
|---|---|
| 111 | Reserved |
| 100 | Reserved |
| 011 | XIP mode is selected (when this mode is entered, the module behaves as if executing in place (XIP), but uses the register data to control timing) |
| 010 | DMA mode is selected |
| 001 | CPU mode is selected (the module is controlled by the CPU in PIO mode. This mode is entered when leaving Boot or XIP mode) |
| 000 | Reserved |