35.6.24 SQI BUFFER DESCRIPTOR DMA TRANSMIT STATUS REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | BDTXDSTAT |
| Offset: | 0x14C |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TXSTATE[3:0] | |||||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | x | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXBUFCNT[4:0] | |||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | x | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXCURBUFLEN[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | x | |
Bits 28:25 – TXSTATE[3:0] Current DMA Transmit State Status bits <3:0>
These bits provide information on the current DMA receive states.
Bits 20:16 – TXBUFCNT[4:0] DMA Buffer Byte Count Status bits <4:0>
These bits provide information on the internal buffer space.
Bits 7:0 – TXCURBUFLEN[7:0] Current DMA Transmit Buffer Length Status bits <7:0>
These bits provide the length of the current DMA transmit buffer.