51.19 Analog-to-Digital Converter (ADC) Electrical Specifications

Table 51-24. ADC AC Electrical Specifications
AC CHARACTERISTICS Standard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial
Param. No. Symbol Characteristics Min. Typ Max. Units Conditions
Device Supply
ADC_1 AVDD ADC Module Supply AVDD(min) — AVDD(max) V VDDIOx = AVDD
Reference Inputs
ADC_3 VREF(4) ADC Reference Voltage (4) The greater of ≥ AVDD(min) or 2.4V (4) — AVDD V VREF ≤ AVDD
Analog Input Range
ADC_7 AFS Full-Scale Analog Input Signal Range (Single-Ended) AVSS — VREF V VREF = AVDD(max)
ADC_9 Full-Scale Analog Input Signal Range (Differential) -VREF — VREF V
Note:
  1. Characterized with an analog input sine wave = (FTP(max) / 100). Example: FTP(max) = 1 Msps / 100 = 10 kHz sine wave.
  2. Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12bit resolution.
  3. ADC is configured in 12bits mode, All registers are at the reset default value unless otherwise stated.
  4. ADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. ADC will function, but with degraded accuracy of approximately ~ ((0,006 * 2^n) / VREF) LSB’s over full scale range, where "n"=#bits. ADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus users application noise/accuracy on AVDD, GNDANA.
  5. Value taken over 7 harmonics.
  6. Value coming from simulation.
Table 51-25. ADC Single Ended Mode AC Electrical Specifications
AC CHARACTERISTICS Standard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
SINGLE ENDED MODE ADC Accuracy
SADC_11 Res Resolution 8 — 12 bits Selectable 8, 10, 12 bit Resolution Ranges
SADC_13 INL (3) Integral Nonlinearity -2 ±1.25 2 LSB 3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
SADC_19 DNL (3) Differential Nonlinearity -1 -0.75 / +1 2 LSB 3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
SADC_25 GERR (3,6) Gain Error -5 — -1 LSB 3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
SADC_31 E0FF (3,6) 0ffset Error 1 — 4 LSB 3.125 Msps Internal VREF = AVDD = VDDIO = 3.3V
SINGLE ENDED MODE ADC Dynamic Performance (1,2)
SADC_43 EN0B (3) Effective Number of bits 10.6 11.2 — bits VREF = AVDD = VDDIO = 3.3V @ 12bit at 3.125 Msps
SADC_45 SINAD (1,2,3) Signal to Noise and Distortion 65 70 — dB
SADC_47 SNR (1,2,3) Signal to Noise ratio 65 70 —
SADC_51 THD (1,2,3,5) Total Harmonic Distortion — -80 -75
Note:
  1. Characterized with an analog input sine wave = (FTP(max) / 100). Example: FTP(max) = 1 Msps / 100 = 10 kHz sine wave.
  2. Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12-bit resolution.
  3. ADC is configured in 12 bits mode, All registers are at the reset default value unless otherwise stated.
  4. ADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. ADC will function, but with degraded accuracy of approximately ~ ((0,006 * 2^n) / VREF) LSB’s over full scale range, where "n"=#bits. ADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus users application noise/accuracy on AVDD and AVSS.
  5. Value taken over 7 harmonics.
  6. Value coming from simulation.
Table 51-26. ADC Differential Mode AC Electrical Specifications
AC CHARACTERISTICS Standard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
DIFFERENTIAL MODE ADC Accuracy
DADC_11 Res Resolution 8 — 12 bits Selectable 8, 10, 12 bit Resolution Ranges
DADC_13 INL (3) Integral Nonlinearity -2 ±1.25 2 LSB 3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
DADC_19 DNL (3) Differential Nonlinearity -1 -0.75 / +1 2 LSB 3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
DADC_25 GERR (3,6) Gain Error -5 — -1 LSB 3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
DADC_31 E0FF (3,6) 0ffset Error 1 — 2 LSB 3.125 Msps, Internal VREF = AVDD = VDDIO = 3.3V
DIFFERENTIAL MODE ADC Dynamic Performance (1,2)
DADC_43 EN0B (3) Effective Number of bits 11.2 11.4 — bits VREF = AVDD = VDDIO = 3.3V @ 12bit at 3.125 Msps
DADC_45 SINAD (1,2,3) Signal to Noise and Distortion 68 70 — dB
DADC_47 SNR (1,2,3) Signal to Noise ratio 68 70 —
DADC_51 THD (1,2,3,5) Total Harmonic Distortion — -84 -80
Note:
  1. Characterized with an analog input sine wave = (FTP(max) / 100). Example: FTP(max) = 1 Msps / 100 = 10 kHz sine wave.
  2. Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12bit resolution.
  3. ADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. ADC will function, but with degraded accuracy of approximately ~ ((0,006 * 2^n) / VREF) LSB’s over full scale range, where "n"=#bits. ADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus users application noise/accuracy on AVDD and AVSS.
  4. Value taken over 7 harmonics.
  5. Value coming from simulation.
Table 51-27. ADC Conversion and Sample AC Electrical Specifications
AC CHARACTERISTICS Standard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
ADC Clock Requirements
ADC_53 TAD ADC Clock Period 20 — 7145 ns VREF = AVDD = 3.3V and Res = 6,8,10 bit
20 — 1250 ns VREF = AVDD = 3.3V and Res = 12 bit
ADC_55 fGCLK_ADCx ADCx Module GCLK max input freq — — FCLK_51 MHz VREF = AVDD = 3.3V
ADC Throughput Rates
ADC_57 FTPR (1) Sample-Rate for ADC with SAMC=1 (min) — — 3.125 Msps 12-bit resolution, Rsource Impedance ≤ 200 Ω
— — 3.571429 10-bit resolution, Rsource Impedance ≤ 250 Ω
— — 4.166667 8-bit resolution, Rsource Impedance ≤ 300 Ω
— — 5 6-bit resolution, Rsource Impedance ≤ 400 Ω
ADC Conversion and Sample Time
ADC_59 TSAMP Sample-Time for ADC 3 — — TAD 12 bit TAD(min), Ext Analog Input Rsource ≤ 200 Ω, Max ADC Clock
3 10 bit TAD(min), Ext Analog Input Rsource ≤ 250 Ω, Max ADC Clock
8 — — 12 bit TAD(min), Ext Analog Input Rsource ≤ 500 Ω, Max ADC Clock
8 10 bit TAD(min), Ext Analog Input Rsource ≤ 700 Ω, Max ADC Clock
14 — — 12 bit TAD(min), Ext Analog Input Rsource ≤ 1 kΩ, Max ADC Clock
14 10 bit TAD(min), Ext Analog Input Rsource ≤ 1.25 kΩ, Max ADC Clock
64 — — 12 bit TAD(min), Ext Analog Input Rsource ≤ 5 kΩ, Max ADC Clock
64 10 bit TAD(min), Ext Analog Input Rsource ≤ 5.5 kΩ, Max ADC Clock
ADC_61 TCNV Conversion Time (after sample time is complete) 13 TAD 12-bit resolution
11 10-bit resolution
9 8-bit resolution
7 6-bit resolution
ADC_63 Twarm-up Warm Up Time after CTRLA.ANAEN=1 and CTRLA.ENABLE=1 — — 500 TAD or 20 µs, which ever is bigger µs
Note:
  1. ADC Throughput Rate FTP = ((1 / ((TSAMP + TCNV) * TAD)) / (# of user active analog inputs in use on specific target ADC module)).

    Specification values assume only one AINx channel in use.