51.18 DFLL/PLL Electrical Specifications

Table 51-22. DFLL (Digital Frequency Locked Loop) AC Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
DFLL48MHz (Open Loop) ^(1,2)
DFLL_1	DFLL_OL_FOUT	DFLL Open Loop Clock Frequency	45.60	48.00	49.12	MHz	Normal Mode (DFLLCTRLA.LOWFREQ=0)
DFLL_1	DFLL_OL_FOUT	DFLL Open Loop Clock Frequency	6.76	8.00	9.20	MHz	Low Frequency Mode (DFLLCTRLA.LOWFREQ=1)
DFLL_9	DFLL_OL_SRT	Start-Up (Ready bit valid)	—	13	16	µs	Normal Mode (DFLLCTRLA.LOWFREQ=0)
DFLL_9	DFLL_OL_SRT	Start-Up (Ready bit valid)	—	68	75	µs	Low Frequency Mode (DFLLCTRLA.LOWFREQ=1)
DFLL48MHz (Closed Loop) ^(3,4)
DFLL_11	DFLL_CL_FIN ⁽⁴⁾	DFLL Closed loop Input Frequency Range	1000	32768	1000000	Hz	—
DFLL_13	DFLL_CL_FOUT ⁽⁶⁾	DFLL Closed Loop Clock Frequency	47.88	48.00	48.12	MHz	Normal Mode (DFLLCTRLA.LOWFREQ=0) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 1465
DFLL_13	DFLL_CL_FOUT ⁽⁶⁾	DFLL Closed Loop Clock Frequency	7.98	8.00	8.02	MHz	Low Frequency Mode (DFLLCTRLA.LOWFREQ=1) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 244
DFLL_15	DFLL_CL_Jitter	DFLL Period Jitter Pk-to-Pk	—	0.92	2.700	%	Normal Mode (DFLLCTRLA.LOWFREQ=0) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 1465
DFLL_17	DFLL_CL_Jitter	DFLL Period Jitter Pk-to-Pk	—	1.0	2.000	%	Low Frequency Mode (DFLLCTRLA.LOWFREQ=1) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 244
DFLL_21	DFLL_CL_SRT^{(5, 6)}	DFLL Closed Loop Mode / Lock Time	—	0.39	0.900	ms	Normal Mode (DFLLCTRLA.LOWFREQ=0) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 1465
DFLL_21	DFLL_CL_SRT^{(5, 6)}	DFLL Closed Loop Mode / Lock Time	—	0.33	1.000	ms	Low Frequency Mode (DFLLCTRLA.LOWFREQ=1) XOSC32 32.768 kHz PPM ≤ 100, DFLLMUL = 244
Note: In Open Loop mode the DFLL uses a self contained internal RC oscillator clock source who's course calibrated value is loaded at out of reset. In addition, there is a fine tune trim register (DFLLTUNE) the user software can assess. Not recommended for functional USB operation, SOF sync start-up only. In Closed loop mode the DFLL can use a variety of clock sources. The DFLL can be trimmed using register DFLLMUL. To insure that the DFLL stays within the +/-0.25% of its clock frequency, any reference clock for DFLL in close loop must be within a 8% maximum error accuracy. REFCLK for DFLL or XOSC32K,PLL is XOSC. DFLLCTRLB.QLDIS = 0: quick lock enabled (default), DFLLCTRLB.CCDIS = 0: chill cycles enabled (default). DFLLMUL.STEP = 8 : Max fine step size, divided or dividing into two parts, search 8 is optimum value. During a maximum of 30 cycles of the reference clock period (250 cycles for 1Mhz), between lock flag asserted and frequency stabilization, DFLL frequency accuracy will be limited to +/-1.5% at 48Mhz (+/-3% at 8Mhz); after this duration, the frequency accuracy is within +/-0.25%. At 1khz reference clock and to maintain the frequency accuracy within +/-0.25% for 48Mhz, a reduced STEP value at 4 (instead of the optimum 8) eliminates this period of inaccuracy, at the expense of maximum 15% of lock time.

Table 51-23. PLL (Frequency Digital Phase Locked Loop) AC Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDDREG=VDDIO=AVDD 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
PLLxxMHz (Fractional Digital Phase Locked Loop)
PLL_1	PLL_FIN	PLL Input Frequency Range	4	—	48	MHz	Over full voltage and temperature operating ranges
PLL_3	PLL_FOUT	PLL Output Clock Frequency	12.7	—	200	MHz	Over full voltage and temperature operating ranges
PLL_11	PLL_SRT⁽⁵⁾	PLL Lock Time	—	25	—	µs	—
Note: In Open Loop mode the DFLL uses a self contained internal RC oscillator clock source who's course calibrated value is loaded at out of reset. In addition, there is a fine tune trim register (DFLLTUNE) the user software can assess. Not recommended for functional USB operation, SOF sync start-up only. In Closed loop mode the DFLL can use a variety of clock sources. The DFLL can be trimmed using register DFLLMUL. To insure that the DFLL stays within the +/-0.25% of its clock frequency, any reference clock for DFLL in close loop must be within a 8% maximum error accuracy. REFCLK for DFLL or XOSC32K,PLL is XOSC. DFLLCTRLB.QLDIS = 0: quick lock enabled (default), DFLLCTRLB.CCDIS = 0: chill cycles enabled (default). DFLLMUL.STEP = 8: Max fine step size, divided or dividing into two parts, search 8 is optimum value. During a maximum of 30 cycles of the reference clock period (250 cycles for 1Mhz), between lock flag asserted and frequency stabilization, DFLL frequency accuracy will be limited to +/-1.5% at 48Mhz (+/-3% at 8Mhz); after this duration, the frequency accuracy is within +/-0.25%. At 1khz reference clock and to maintain the frequency accuracy within +/-0.25% for 48Mhz, a reduced STEP value at 4 (instead of the optimum 8) eliminates this period of inaccuracy, at the expense of maximum 15% of lock time.