40.127 GMAC Transmit Schedule Control Register
| Name: | GMAC_TSCTL |
| Offset: | 0x580 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXSQ2[1:0] | TXSQ1[1:0] | TXSQ0[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 0:1, 2:3, 4:5 – TXSQx Transmit Schedule for Qx
| Value | Description |
|---|---|
| 0 | Fixed priority |
| 1 | CBS Enabled only valid for top two enabled queues and if CBS capability selected. |
| 2 | DWRR enabled |
| 3 | ETS enabled |