SAMA5D29

53.6.47 MCAN TSU Timestamp Status 1

Name:	MCAN_TSU_TSS1
Offset:	0x168
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24
	TSL[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	TSL[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TSN[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TSN[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – TSL[15:0] Timestamp Lost

Each timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related timestamp register was overwritten before it was read. Reading a timestamp register resets the related bit.

Bits 15:0 – TSN[15:0] Timestamp New

Each timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related timestamp register. Reading a timestamp register resets the related bit.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.