6.5 Performance Monitor Unit (PMU)

The performance monitor provides a method to analyze code efficiency, and allows software routines that incur processor stalls to be identified and optimized. In the PIC32AK1216GC41064 family of devices, the architecture does not have a fixed relationship between the CPU clock speed in MHz and the throughput of the CPU in MIPS (Million Instructions per Second). The throughput of the CPU is dependent on extra cycles incurred from the following:

• CPU pipeline data dependency
• Branches or program flow changes
• Cache misses
• Slow memory or SFR accesses
• Arbitration between bus masters
• A bus that is slower than the CPU

The performance monitor counts the events that cause extra cycles to be inserted into the program flow and the number of elapsed clock cycles. Using this information, the cycles-per-instruction (CPI) can be calculated and the reasons for poor code efficiency can be determined. The CPI value is the number of elapsed clock cycles divided by the number of opcodes that were executed. The stall cycle types listed above will increase the CPI.

The performance monitor uses a set of event signals from the CPU to determine stalls. The module features eight 64-bit counters that can be independently configured to count the occurrence of events from Table 6-30.