6.1 Architectural Overview

The CPU has 32-bit (data) modified Harvard architecture with a 5-stage instruction pipeline, single phase clock design, with 32-bit instructions.

The CPU has a 32-bit instruction word with a variable length opcode field. The CPU also supports some instructions that are only available in 16-bit format. The Program Counter (PC) is 24 bits wide to access a 16MB (24-bit address) unified linear address map.

The CPU supports up to eight addressing modes. A 5-stage fully interlocked instruction pipeline with reduced branch latency and hardware mitigated pipeline hazard stalls helps maintain throughput and provides predictable execution. Most instructions execute in a single-cycle effective execution rate, with the exception of instructions that change the program flow. A hardware program loop construct is supported by the overhead free REPEAT instruction, which is interruptible at any point. For loops greater than one instruction, the DBT (Decrement Test and Branch) instruction may be used to reduce loop overhead.

The CPU supports High Performance Math Support with a tightly coupled 16/32-bit Integer and a Fixed-Point fractional DSP engine with a 72-bit shifter, saturation and rounding support. There is an optional common issue Single and Double Precision Floating Point Unit (FPU) coprocessor with an independent load-store execution pipeline.

CPU Supports closely coupled coprocessor macros with the following features:

• Decode and issue from the CPU pipeline into independent coprocessor pipeline(s)
• Pipeline hazards detected and mitigated in both the CPU and coprocessor(s)
• Dedicated data move and conditional coprocessor status branch instructions
• Coprocessor interrupt support

Figure 6-1 illustrates the CPU block diagram.