6.4 Prefetch Branch Unit (PBU)
The Prefetch Branch Unit (PBU) in the PIC32A core devices accelerates the interface between the Program Flash Memory (PFM) and the CPU instruction bus. The PBU can predictively prefetch the next sequential address and cache fetched program data that are the target of a CPU instruction fetch.
PBU in PIC32A core devices supports the following functions:
- PBU accelerates the execution of linear program code flow.
- As cache accelerates, the execution of non-linear program flow changes (branches).
The PBU in the PIC32A core devices have the following features:
- Provides an interface between the PFM and the CPU instruction bus
- Instruction Stream Buffers for prefetching and caching of linear PFM instruction flows
- Instruction Cache for caching of the most frequently hit target instructions
- Provides parity checks on program data stored in the Instruction Cache to ensure data integrity
The PBU block diagram in Figure 6-16 shows data paths to and from the PBU in the PIC32A environment. The PBU provides data when the CPU fetches program data from Flash memory. It may provide program data from an internal buffer, or fetch program data from Flash if the requested program data is not available. Flash fetch operations are therefore accelerated when data are sourced from internal PBU buffers.