19.5.2 Hysteretic Control for LED Drivers

The hysteretic control offers the fastest response to the changing parameters, such as voltage or current. The hysteretic control finds wide usage in LED applications, where the current is required to be in a limited range around the average value. The disadvantage of the hysteretic topology is the variable frequency of operation. Figure 19-9 shows an example circuit where the LED current is controlled to an average value with a tolerance decided by the register values.

Figure 19-9. Hysteretic Control for LED Drivers

The comparator uses Hysteretic mode for such applications. The Hysteretic mode is controlled by the HME bit in the SLPxCON register. In order to enable the Hysteretic mode, the HME bit must be set to ‘1’ and the SLOPEN bit is cleared. The upper limit of the hysteretic control is defined by DACDAT, while the lower limit is defined by DACLOW. In Hysteretic mode, the comparator module has a pair of output signals that are available as Peripheral Pin Select (PPS) inputs: PWM_Req_on and PWM_Req_off. These signals can then be mapped to the PWM PCI input for controlling the PWM outputs. The DAC settings for Hysteretic mode are shown in DAC Settings for Hysteretic Mode.

DAC Settings for Hysteretic Mode

	/* Clock Selection */
    PCLKCONbits.MCLKSEL = 3;        // Master Clock Source is APLL
    PG1CONLbits.CLKSEL = 1;         // Clock selected by MCLKSEL
    while(!_APLLCK)                 // Wait for PLL lock
    PG1IOCONHbits.PENH = 1;         // Enable H output
    PG1IOCONHbits.PENL = 1;         // Enable L output    
    PG1IOCONLbits.FFDAT = 0b11;     // FF PCI data is 0b11
    // PPS setup
    RPINR12bits.PCI8R = 168;        // 'PWM_Req_On' from DAC to PCI8
    RPINR12bits.PCI9R = 169;        // 'PWM_Req_Off' from DAC to PCI9    
    // FF PCI setup
    PG1FFPCILbits.TSYNCDIS = 1;     // Terminate immediately
    PG1FFPCILbits.TERM = 0b111;     // PCI 9 (PWM_Req_Off)
    PG1FFPCILbits.PSS = 8;          // PCI 8 (PWM_Req_On)
    PG1FFPCIHbits.ACP = 0b100;      // Latched rising edge
    PG1CONLbits.ON = 1;             // Enable PG1
    // DAC initialization 
    DAC1DATbits.DACLOW = 0x400;     // Lower cmp limit, 0.825 V
    DAC1DATbits.DACDAT = 0xC00;     // Upper cmp limit, 2.475 V
    DAC1CONbits.CBE = 1;            // Enable comparator blanking 
    DAC1CONbits.TMCB = 100;         // 2/500 MHz * 100 = 400 nS
    SLP1CONbits.HCFSEL = 1;         // 1 = PWM1H 
    SLP1CONbits.HME = 1;            // Hysteretic Mode
    DAC1CONbits.INSEL = 1;          // CMP1B input
    DAC1CONbits.DACOEN = 1;         // Output DAC voltage to DACOUT1 pin
    DAC1CONbits.DACEN = 1;          // Enable DAC module 
    DACCTRL1bits.DACON = 1;         // Enable DAC1