22.5 Interrupts

The SPI module has the ability to generate interrupts reflecting the events that occur during the data communication. The following types of interrupts can be generated:

• Transmit buffer empty interrupts are signaled by SPIxTXIF. This event occurs when:
  • TX watermark interrupt
  • SPITUR = 1
  • SPITBF = 1
  • SPITBE = 1, provided respective mask bits are enabled in SPIxIMSK
• General interrupts are signaled by SPIxIF. This event occurs when:
  • FRMERR = 1
  • BUSY = 1
  • SRMT = 1, provided respective mask bits are enabled in SPIxIMSK

All of these interrupt flags, which must be cleared in software, are located in the IFSx registers. Refer to the “Interrupt Controller” chapter for details.

To enable the SPIx interrupts, use the respective SPIx Interrupt Enable bits, SPIxRXIE, SPIxTXIE and SPIxIF, in the corresponding IECx registers.

The Interrupt Priority Level (IPL) bits must be also be configured using the SPIxIP bits in the corresponding IPCx registers.

When using Enhanced Buffer mode, the SPIx transmit buffer can be configured to interrupt at different FIFO levels using mask bits, TXMSK[2:0] in SPIxIMSK[18:16]. Also, the Transmit Watermark Interrupt bit, TXWIEN (SPIxIMSK[23]), should be enabled.

Similarly, the SPIx receive buffer can be configured to interrupt at different FIFO levels using mask bits, RXMSK[2:0] (SPIxIMSK[26:24]). Also, the Receive Watermark Interrupt, RXWIEN (SPIxIMSK[31]), should be enabled.