17.5.4 Cycle-by-Cycle Current Limit Mode

Cycle-by-Cycle Current Limit mode is a widely adopted control strategy for power applications and motor control. Current is measured and limited to a predetermined level using the internal comparator module. Cycle-by-Cycle Current Limit mode control for BLDC motors can automatically limit motor phase currents to a predetermined maximum value, using a comparator to provide an input to the PCI block. This has the advantage of allowing operation to continue when the limit is reached, rather than triggering a Fault. The PWM is configured as follows:

  • Independent Edge PWM mode
  • Complementary Output mode
  • Self-Triggered mode

The current limit PCI block logic is used to control the cycle truncation. The Leading-Edge Blanking feature is used to filter out switching transients and slightly delay cycle truncation, as shown with the upper arrows in Figure 17-45. The duty cycle is truncated when the PCI active signal goes high.

To reset the PCI block for the next cycle, the PCI terminator is configured to detect the falling edge of the comparator (CMP1 Out). The terminator signal is then synchronized to the End-of-Cycle (EOC) and the PCI active signal is reset, as shown with the lower arrows in Figure 17-45.

Figure 17-45. Timing Diagram for Self-Triggered, Complementary Output and Current Limit Cycle-by-Cycle PWM Modes

Cycle-by-Cycle Current Limit Mode

void PWMInitialization(void);
void enable_CMP1();

int main() {
    
    PWMInitialization();
    
    //The CMP1A input will be compared against the DAC1 output to create the CMP1 out signal.
    //If CMP1A > DAC output, PWM1 output will be overridden
    //If CMP1A < DAC output, PWM1 ourput will be active
    
    while(1);
    
    return 0;
}

void PWMInitialization(void) {
    
    configure_PLL2_Fout_200MHz_and_VCODIV_500_MHz();
    clock_PWM_from_PLL2_Fout();
    initialize_CMP1_and_clock_from_PLL2_VCODIV();
    
    PG1CONbits.CLKSEL = 1;      //PWM generator 1 uses the PWM master clock, undivided and unscaled
    PG1CONbits.MODSEL = 0b000;  //PWM generator 1 uses independent edge PWM mode
    PG1CONbits.TRGMOD = 0b00;   //PWM generator 1 uses single trigger mode
    PG1CONbits.UPDMOD = 0b000;  //Update data registers at SOC
    
    //PWM Generator 1 uses PG1DC, PG1PER, PG1PHASE registers
    PG1CONbits.MDCSEL = 0;
    PG1CONbits.MPERSEL = 0;
    PG1CONbits.MPHSEL = 0;
    
    PG1CONbits.MSTEN = 0;       //PWM Generator does not broadcast UPDATE status bit state or EOC signal
    PG1CONbits.SOCS = 0b0000;   //Start of cycle (SOC) = local EOC
       
    PG1IOCONbits.PMOD = 0b00;   //PWM Generator 1 outputs operate in Complementary mode
    
    //PWM Generator 1 controls the PWM1H and PWM1L output pins
    PG1IOCONbits.PENH = 1;
    PG1IOCONbits.PENL = 1;
    //PWM1H and PWM1L output pins are active high
    PG1IOCONbits.POLH = 0;
    PG1IOCONbits.POLL = 0;
    //Current limit data: 1 on PWM1L and 0 on PWM1H
    PG1IOCONbits.CLDAT = 0b01;

    
    //Given the 200MHz PWM clock, this period will result in a PWM frequency of 100kHz
    PG1PER = (2000 << 4);           //Time units are 1/16 of a PWM clock
    PG1DC = (1000 << 4);            //50% duty cycle
    PG1PHASE = (200 << 4);          //200 PWM clocks of phase offset in rising edge of PWM
    PG1DTbits.DTH = (40 << 4);      //40 PWM clocks of dead time on PWM1H
    PG1DTbits.DTL = (40 << 4);      //40 PWM clocks of dead time on PWM1L
    PG1LEBbits.PHR = 1;             //Rising edge of PWM1H will trigger the LEB counter
    PG1LEBbits.LEB = (100 << 4);    //100 PWM clocks of LEB
    
    //PCI logic configuration for current limit cycle by cycle mode, comparator 1 output as PCI source
    PG1CLPCIbits.TERM = 0b001;      //Terminate when PCI source transitions from active to inactive
    PG1CLPCIbits.TSYNCDIS = 0;      //Termination of latched PCI delays till PWM EOC (for Cycle by cycle mode)
    PG1CLPCIbits.AQSS = 0b010;      //LEB active is selected as acceptance qualifier
    PG1CLPCIbits.AQPS = 1;          //LEB active is inverted to accept PCI signal when LEB duration is over
    PG1CLPCIbits.PSYNC = 0;         //PCI source is not synchronized to PWM EOC so that current limit resets PWM immediately
    PG1CLPCIbits.PSS = 0b11011;     //Comparator 1 output is selected as PCI source signal
    PG1CLPCIbits.PPS = 0;           //PCI source signal is not inverted
    PG1CLPCIbits.ACP = 0b011;       //latched PCI is selected as acceptance criteria to work when CMP1 out is active
    PG1CLPCIbits.TQSS = 0b0000;     //No termination qualifier used so terminator will work straight away without any qualifier
    
    //Enable PWM generator 1
    PG1CONbits.ON = 1;
}