13.9 Non-Maskable Traps

Traps are non-maskable, nestable interrupts that adhere to a fixed priority structure. Traps provide a means to correct erroneous operation during debugging and the operation of the application. If the user application does not intend to correct a trap error condition, these vectors must be loaded with the address of a software routine to reset the device. Otherwise, the user application must program the trap vector with the address of a service routine that corrects the trap condition.

The following sources of non-maskable traps are implemented in PIC32A devices:

  • Bus error and ECC DED trap
  • Illegal opcode error trap
  • CPU address error trap
  • CPU stack error trap
  • CPU math error trap
  • Generic trap

For many of the trap conditions, the instruction that caused the trap is allowed to complete before exception processing begins. Therefore, the user application may have to correct the action of the instruction that caused the trap. Each trap source has a fixed priority as defined by its position in the IVT/IVTC. A bus error trap has the highest priority, while a generic trap has the lowest priority. Refer Table 13-59 for trap vector and priority details.