13.2 Architectural Overview

The interrupt controller module assembles all the interrupt request signals from the peripherals and assigns both a fixed “natural order” priority and a user assigned priority to each signal. The highest level unmasked interrupt request is then presented to the processor core along with a vector number, which represents an offset into the IVT.

The interrupt controller provides interrupt sources that can be programmed with different priority levels along with six processor traps and other generic traps.